RISC-V International and CHIPS Alliance have announced a joint collaboration to update the OmniXtend Cache Coherency specification and protocol, along with building out developer tools for OmniXtend.
As part of the collaboration, RISC-V International and CHIPS Alliance have formed a new OmniXtend working group which will focus on creating an open, cache coherent, unified memory standard for multicore compute architectures. OmniXtend is a fully open networking protocol for exchanging coherence messages directly with processor caches, memory controllers and various accelerators, providing an efficient way of attaching new accelerators, storage and memory devices to RISC-V systems on chip (SoCs). It can be used to create multi-socket RISC-V systems.
The group will update the OmniXtend specification and protocol, build out architectural simulation models and a reference register-transfer level (RTL) implementation, as well as create a verification workbench. These tools for an open, standard unified memory coherency bus leveraging OmniXtend will make it easier for designers to take advantage of OmniXtend for data-centric applications.
“As RISC-V International develops implementation independent specifications and ecosystem components, it is an important priority for us to ensure that whatever we develop will work with emerging and established standards. The joint working group will interact with various RISC-V groups to review the OmniXtend protocol with an emphasis on cache management and paying close attention to coherency enablement for RISC-V members,” said Mark Himelstein, CTO at RISC-V International. “As a result of this joint effort, the RISC-V community will have the tools they need to leverage an open, coherent, unified memory standard for all types of data-centric applications.”
“The newly formed OmniXtend working group will set the standard for open, coherent heterogeneous compute architectures. We plan to allow for a mixture of hardware IP blocks, giving developers more design flexibility so they can choose what works best for their specific application needs,” said Rob Mains, general manager at CHIPS Alliance. “We encourage the RISC-V community to get involved in this important initiative which will open new design possibilities with OmniXtend.”
Fast track architecture extension process
Last month, RISC-V International made it easier to standardize small architecture-extension proposals, with a fast track process. This fast track process is a means to create a relatively small architecture extension without creating a task group. The proposed extension should be of a straightforward nature that is of value to a significant portion of the RISC-V community. It should address a specific and clear-cut issue or need, cleanly fit into the existing architecture and current solid draft extensions, and not be subject to contention.
The “Fast Track Architecture Extension Process” (Fast Track) defines the process for developing and standardizing architecture extensions that meet specific criteria, while providing reasonable quality control under the oversight and approval of the relevant RISC-V standing committee. Once an extension has been submitted for consideration it will undergo an internal review before entering a 45-day public review process.
Himelstein commented, ““The Fast Track system enables us to more quickly address the needs of the RISC-V community as the diversity of RISC-V solutions and applications continues to grow exponentially.”
The ZiHintPause extension, which enables engineers to reduce the energy consumption of their designs, is the first to be ratified under this new process. The extension also helps improve the performance of spin-wait loops and enable multithreaded cores to temporarily relinquish extension resources. The ZiHintPause extension adds a single PAUSE instruction (encoded as a HINT instruction) to the ISA. Himelstein said, ““The ratification of ZiHintPause demonstrates how this simplified process significantly accelerates the review of important extensions, while still maintaining RISC-V’s core tenant of openness with a public review period.”
“This is an important extension for the RISC-V ISA, so we are happy to see that ZiHintPause was able to be ratified quickly and is now available for the whole RISC-V community to use,” said Greg Favor, co-founder and CTO, Ventana Micro Systems. “Fast Track maintains the necessary checks and balances to ensure extensions are properly designed and adhere to RISC-V’s architectural approach, while paving the way for RISC-V International to rapidly expand its set of standardized extensions.”
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