A few weeks ago, I attended the Xilinx Worldwide Sales Conference. Besides the opportunity to stay in a hotel where part of the Arnold Schwarzenegger film True Lies was filmed, this was a great opportunity to go hands-on with new tools and boards in a number of lab sessions.
One of my favorite labs was the PYNQ RFSoC lab, which I thought really demonstrated the RFSoC and its capabilities. This lab outlined not only the RF converter capabilities but also those of the SDFEC and even outlining how Python can be used for digital signal processing on the processing system (PS). Of course, the lab swiftly followed up with how the DSP algorithm could be accelerated using PYNQ and programmable logic overlays.
I was happy to see the inclusion of these labs in the latest PYNQ V2.4.1 release for the ZCU111. So, I thought I would dig out my ZCU111 and rerun the lab and share some of the most interesting results.
Along with the new RFSoC overlay and associated notebooks, the RFSoC PYNQ labs changes how we interact with the Jupyter environment as well. Instead of using the standard Jupyter interface that we will be familiar with from our previous PYNQ adventures, and is shown below
We use the Jupyter Labs interface, which we access by adding the /lab address to the standard pynq:9090 (http://pynq:9090/lab). This opens up a range of new features for developing and running our PYNQ applications.
Upon first glance, Jupyter lab appears much more like a traditional IDE, and includes new features such as the ability to drag and drop cells between note books and associate terminals with notebooks for scratch outputs.
The use of Jupyter labs is not only limited to this set of labs; in fact, we can use labs on any PYNQ image by going to Pynq:9090/lab.
Once we have Jupyter labs up and running, under the RFSoC_Workshop folder you will see five notebooks.
Introduction — Basic introduction to working with PYNQ and Jupyter notebooks.
PYNQ & Data Converter — QPSK signal generation and reception using the data converters under control of the PYNQ framework.
PYNQ & SDFEC — Low Density Party Check (LDPC) encoding and decoding to demonstrate the ability of the Soft Decision Forward Error Correction Integrated block to demonstrate how the RFSoC can work in noisy environments.
DSP and Python — Introduction to DSP with Python.
DSP and PYNQ — Introduction to DSP with PYNQ.
For the remainder of the blog, we will be examining the PYNQ & Data Converter as well as PYNQ & SDFEC notebooks.
To make use of this notebook on the ZCU111, we need to connect J4 to J5 on the RF FMC breakout board which enables us to loop back the RF converters.
Once downloaded, the PYNQ overlay lets us generate QPSK signals in the PL and transmit them via the RF data converter as shown in the diagram below. The points marked with dotted lines in the diagram enable us to visualize the waveforms in the Jupyter notebook at points in the processing chain.
For example, ol.qpsk_tx_get_symbols() call provides us with information that allows us to generate the following plot.
We can see both the time and frequency domain plots using the get shaped FFT and get shaped time call — these are the signals the RFSoC transmits.
Of course, we want to be able to receive the RF signal and decode the data contained within it. Examining the RF Receive path we can see the same ability to observe the signal at various points in the processing chain.
Here, we can look at the decimated time and frequency domain along with a unsynchronized constellation diagram.
Once these raw signals have been received, we can synchronize the output data and see the final constellation.
For me, the ability to visualize the inspect the different stages of the transmit and receive processing chain is very interesting and offers an understanding of the RF data converters. Once we have run through these base settings, we can even use the Jupyter notebook to customize the TX and RX chain to explore the impacts of changing NCO frequencies, etc. and again observe the effects at different points in the processing chain.
The second notebook PYNQ & SDFEC allows us to see the performance of the Soft Decision Forward Error Correction block and contains the architecture below.
One of the great things about this notebook is that it allows us to see the performance of SDFEC for several different modulation schemes and codes. These tests take a few minutes to run but once the completed you can see the performance of the SDFEC across different modulations and LDPC codes.
As you can see below the results for the SDFEC across different modulation schemes plot the error vs SNR (dB). For each of the schemes 200, 40 Mb blocks are passed through the SDFEC.
The performance of the SDFEC in the RFSoC example can be correlated against the IP performance specified in the product guide, but you can see the more complex the modulation scheme the more susceptible it is to noise. The SNR also impacts the throughput we can achieve.
Running the SDFEC again using different LDPC codes, we can see in the results the system level trade off between throughput and bit error rate.
One of the final tests in the lab is to report the throughput for a QAM64 modulation scheme. When this is checked against the predicted DOCSIS short performance, this is close to the prediction
While this blog has been a whistle stop tour of the RFSoC workshop, hopefully it shows the benefits of using PYNQ with the RFSOC and the capabilities provided by both the RF converters and the SDFEC.
You can find out more about the RFSoC workshop via the link below.