This week, we are going to examine how we can do the same when we use a standard FPGA. For this example, we are going to use a Artix-A7 100T device running a MicroBlaze design. The program executed by the MicroBlaze will be different depending upon the image.
Again, we will be creating two images — one gold image that can be fallen back to, and another which can be overwritten and updated if required in the field.
The inclusion of the gold image means that if the update goes wrong, we will not brick the system. However, to ensure this operates correctly, we need to correctly configure the design and especially the constraints.
So how does it work? In normal operation (no MultiBot), the bitstream located at address 0x0 in the configuration memory is loaded. In a MultiBoot approach, there are two images in the configuration memory device. The first is located at 0x0 and is the gold image, while the normally loaded image is stored at an offset in the configuration memory.
Crucially the gold image contains the address offset where the normal / update image resides. The address of this normal / update image is read from the gold image and stored in the gold image Warm Boot Start Address (WBSTAR). The configuration block in the FPGA can then jump to this memory address using the IPROG or internally generate pulse which initiates the jump to the specified address.
Should a configuration error be detected in the normal / update bitstream, the FPGA will fall back to using the gold image.
The two images I am creating for this demonstration will print out different ‘hello world’ messages depending upon if the gold or update image is loaded.
Besides the difference in the contents of the MicroBlaze program, the main difference between projects in the MultiBoot configuration is in the constraints files.
Within the constraints file for the gold image, we need to enable the fallback option. We also need to provide the location of the update image, which should be attempted to be loaded first.
I have also enabled compression on the image and set the SPI bus width to 1.
While for the update image, its constraint file should be as below enabling the configuration fallback but without the config address specified.
Once we have both images (gold and update), we can then generate a combined MCS file which contains both images — with the gold image at address 0 and the update image at the specified offset. Note: in the field update would require the FPGA to contain a configuration method to write a bin or hex file to the configuration memory at the update address.