The Arm Cortex cores are everywhere. I like (and use) them a lot. Don’t take me wrong: maybe Arm needs some competition? It is very refreshing to see that something new is getting a lot of attention: RISC-V!
However, a new RISC-V player emerged: OpenISA. On that site, there was an offer for a free board for which I applied. I nearly have forgotten about this, but after several weeks afterwards I received two boards. The website and discussions in the communities indicated it, and the logo on the device confirmed it: it is Freescale (well, now NXP) which produced that device. What they have done is create a community page on open-isa.org and this where the board ‘getting started’ points to, and what I have used to set up my environment. It seems that NXP has started a kind of test run ‘under the radar,’ which is interesting on its own.
VEGA RV32M1 Board
Compared to the SiFive board, I’m happy to report that the VEGA RV32M1 can be debugged properly with a 10-pin SWD/JTAG connector.
The board is very similar to other ‘FRDM’ (or Freedom) boards from Freescale/NXP. It features an NXP Kinetis K26 as UART (and possibly debug? I did not find a firmware) bridge.
So I used a SEGGER J-Link Mini to debug the board.
There are four cores (plus the Kinetis K26) on the board. Which core to boot is selectable, but I have not explored that yet.
Because each half (RI5CY/M4F and Zero-RISCY/M0+) share the same bus, it is more like a dual-heterogeneous core setup. Interestingly, the two RISC-V cores are from the PULP project at the ETH Zurich.
The ‘getting started’ guide provides videos and basic steps to set up an environment, explaining it for using make files or with a DIY Eclipse IDE. I decided to use the NXP MCUXpresso IDE instead, and that worked very well. I used the MCUXpresso IDE V10.3.1 in this article, and it needs only the GNU MCU Eclipse plugins and a toolchain to develop for RISC-V.
Drag and drop the .project file into the IDE. Because the projects in the SDK are using project relative links, I have to ‘link’ to it:
With the toolchain setup correctly, this should build fine:
The projects include launch configurations for OpenOCD (Menu Run > Debug Configurations). Verify that the correct openOCD binary is used with its configuration file:
Power the board with the J8 USB connector:
With this, hit ‘Debug’ and I am debugging.
Using a RISC-V core, or as in this case using multiple ones is fun, and I’m glad to see that software and tools are evolving. RISC-V could be the next big thing, but for sure it might take a while to be widely available. According to this EE Journal article, more boards might be available in the future.
What’s next? There is a new FreeRTOS release available for RISC-V, so I’m going to try that one…