Debugging the RV32M1-VEGA RISC-V with Eclipse and MCUXpresso IDE




The Arm Cortex cores are everywhere. I like (and use) them a lot. Don’t take me wrong: maybe Arm needs some competition? It is very refreshing to see that something new is getting a lot of attention: RISC-V!

RV32M1 (VEGAboard)

RISC-V is an open instruction set architecture, and so far SiFive was *the* vendor offering real chips. I’m already using a RISC-V from SiFive (see Open Source RISC — Eclipse with RISC-V on the SiFive HiFive1 Board).

However, a new RISC-V player emerged: OpenISA. On that site, there was an offer for a free board for which I applied. I nearly have forgotten about this, but after several weeks afterwards I received two boards. The website and discussions in the communities indicated it, and the logo on the device confirmed it: it is Freescale (well, now NXP) which produced that device. What they have done is create a community page on open-isa.org and this where the board ‘getting started’ points to, and what I have used to set up my environment. It seems that NXP has started a kind of test run ‘under the radar,’ which is interesting on its own.

VEGA RV32M1 Board

Compared to the SiFive board, I’m happy to report that the VEGA RV32M1 can be debugged properly with a 10-pin SWD/JTAG connector.

Top of VEGAboard
Bottom of VEGAboard

The board is very similar to other ‘FRDM’ (or Freedom) boards from Freescale/NXP. It features an NXP Kinetis K26 as UART (and possibly debug? I did not find a firmware) bridge.

MK26

So I used a SEGGER J-Link Mini to debug the board.

There are four cores (plus the Kinetis K26) on the board. Which core to boot is selectable, but I have not explored that yet.

VEGAboard Block Diagram (📷: EE Journal)

Because each half (RI5CY/M4F and Zero-RISCY/M0+) share the same bus, it is more like a dual-heterogeneous core setup. Interestingly, the two RISC-V cores are from the PULP project at the ETH Zurich.

Installation

The ‘getting started’ guide provides videos and basic steps to set up an environment, explaining it for using make files or with a DIY Eclipse IDE. I decided to use the NXP MCUXpresso IDE instead, and that worked very well. I used the MCUXpresso IDE V10.3.1 in this article, and it needs only the GNU MCU Eclipse plugins and a toolchain to develop for RISC-V.

rv32m1 SDK and Toolchain
  • Run the installer for the RISC-V SDK and install it into c:vega (which is the default).
  • Install RISC-V SDK.
  • Optionally: Install the Arm SDK into the same folder as above.
  • Create a folder ‘Toolchain’ in C:Vega and extract the two zip files from the Toolchain zip/archive into it.
  • Toolchain zip files.
  • Extract the content of openocd.zip into a folder named openocd.
  • Extract the content of the riscv32-unknown-elf-gcc.zip into a folder named riscv32-unknown-elf-gcc
  • The installation structure should now look like this:
VEGA Installation Folder
GNU MCU Eclipse Build Tools
GNU MCU Eclipse Plugins

With this, all the plugins and tools are installed.

Debug Probe

I’m using a J-Link EDU Mini. There are three SWD/JTAG headers on the board: use the one near the RV32M1 microcontroller.

The toolchain comes with a pre-built OpenOCD package which works with a SEGGER J-Link (see https://wiki.segger.com/OpenOCD). To use it, launch the UsbDriverTool:

UsbDriverTool

Then install WinUSB on the J-Link driver. For this, the J-Link has to be plugged into the host:

Install WinUSB

NOTE: By doing this, I cannot use the J-Link probes with the SEGGER J-Link software anymore. To use the J-Link again the ‘normal’ way, I have to restore the default driver again:

Restore Default Driver

Eclipse Toolchain Setup

In the MCUXpresso IDE, verify that the toolchain settings in the workspace settings (menu Window > Preferences):

Global Build Tools Path:

C:VegaGNU MCU EclipseBuild Tools2.11-20180428-1604bin
Global Build Tools Path

RISC-V Toolchain:

C:VegaToolchainriscv32-unknown-elf-gccbin
RISC-V Toolchain

OpenOCD:

C:VegaToolchainopenocdbin
Global OpenOCD Path

Importing Project

Import a project from the SDK, e.g:

C:Vegarv32m1_sdk_riscvboardsrv32m1_vegademo_appsbubbleri5cyriscveclipse

Drag and drop the .project file into the IDE. Because the projects in the SDK are using project relative links, I have to ‘link’ to it:

Importing Project

With the toolchain setup correctly, this should build fine:

Building Project

Debugging

The projects include launch configurations for OpenOCD (Menu Run > Debug Configurations). Verify that the correct openOCD binary is used with its configuration file:

OpenOCD Settings

Power the board with the J8 USB connector:

Debugging VEGAboard

With this, hit ‘Debug’ and I am debugging.

Debugging VEGAboard with Eclipse and OpenOCD

Summary

Using a RISC-V core, or as in this case using multiple ones is fun, and I’m glad to see that software and tools are evolving. RISC-V could be the next big thing, but for sure it might take a while to be widely available. According to this EE Journal article, more boards might be available in the future.

What’s next? There is a new FreeRTOS release available for RISC-V, so I’m going to try that one…

Happy RISCing!

Originally published at mcuoneclipse.com on March 4, 2019.


Debugging the RV32M1-VEGA RISC-V with Eclipse and MCUXpresso IDE was originally published in Hackster Blog on Medium, where people are continuing the conversation by highlighting and responding to this story.

Original article: Debugging the RV32M1-VEGA RISC-V with Eclipse and MCUXpresso IDE
Author: Erich Styger